1. Field of the Invention
This invention relates to a semiconductor device, especially to a DMOS (diffused MOS) type transistor.
2. Description of the Related Art
A DMOS type high withstand voltage MOS transistor has a high source-drain breakdown voltage or a high gate breakdown voltage. It has been broadly used in driver such as LCD driver as well as in power source circuit. Especially, a MOS transistor with a high source-drain breakdown voltage (BVds) and a low on resistance has been sought after in recent years.
FIG. 5 is a cross-sectional view showing the configuration of an N channel type high withstand voltage MOS transistor of prior arts. An N type epitaxial layer 101 is disposed on the surface of a P-type semiconductor substrate 100. An N+ type buried layer 102 is formed on the interface between the epitaxial layer 101 and the semiconductor substrate 100. A gate electrode 104 is formed on the epitaxial layer 101 with a gate insulation film 103 between them. A P-type body layer 105 (SP+D, P+D) is formed on the epitaxial layer 101 and an N+ type source layer 106 (NSD) is disposed on the surface of the body layer 105 adjacent to the gate electrode 104.
An N+ type N well layer 107 (N+W) is formed on the surface of the epitaxial layer 101, and an N+ type drain layer 108 (NSD) on the surface of N well layer 107. The region on the epitaxial layer 101 between the drain layer 108 and the body layer 105 is a drift region 109. A depletion layer expands in the drift region 109 and a P+L layer 110 made of P-type impurities is formed in the depletion layer in order to improve the strength against high voltage of the drain. The region on the surface of the body layer 105 between the drift region 109 and the source layer 106 is a channel region CH.
A first interlayer insulation film 111 is disposed on the surface of the semiconductor substrate 100. A first field plate 112 extending from above a part of the gate electrode 104 to above the P+L layer 110 is formed on the first interlayer insulation film 111. Also, a second interlayer insulation film 113 is disposed on the first interlayer insulation film 111. A second field plate 114 extending from above a part of the first field plate 112 to above the P+L layer 110 is formed on the second interlayer insulation film 113.
The first and second field plates 112, 114 are made of conduction material such as aluminum or poly-silicon. The electric potential of these plates are set as the same as that of the drain layer 106. The drain electric field is eased by the expansion of the depletion layer in the drift region 109, leading to the improved withstand voltage.
A P+ type potential fixation layer 115 (PSD, P+) for fixing the electric potential of the body layer 105 is formed right next to the source layer 106. A field insulation film 116 is disposed in a region extending from the P+L layer 110 to the drain layer 108 on the epitaxial layer 101 by using LOCOS methods. Also, a wiring layer 117 made of, for example, aluminum is formed over the source layer 106, the drain layer 108 and the potential fixation layer 115.
It is possible to acquire the high source-drain breakdown voltage BVds (for example 260-300 voltage) from the high withstand voltage MOS transistor with the configuration described. The high withstand voltage MOS transistor of prior arts is called a transistor D, hereinafter, for the sake of convenience.
The related technologies are published in Japanese Patent Application Publication No. 2004-039774.
Although it is possible to acquire the high withstand voltage MOS transistor of prior arts (transistor D), a MOS transistor with smaller on resistance and higher current driving capacity has been sought after.